The present invention relates to a semiconductor integrated circuit.
Recently, along with the miniaturization of devices, the integration density of semiconductor integrated circuits has increased. Semiconductor integrated circuits often use CMOS circuits that can realize low-power logic circuits with a relatively small number of devices. A CMOS circuit is constituted by a combination of MOS transistors of the first conductivity type (e.g., PMOS transistors) and MOS transistors of the second conductivity type (e.g., NMOS transistors).
FIG. 11 shows an example of a conventional planar layout that realizes an inverter serving as a basic gate in a CMOS circuit. A PMOS transistor region 101 and NMOS transistor region 102 are arranged on a surface portion of a semiconductor substrate. A gate electrode 103 made of a polysilicon film or the like extends across both the channel regions of the regions 101 and 102.
The following wirings are formed on the source and drain regions of the regions 101 and 102 through an interlayer dielectric film (not shown): a wiring 104a for connecting the source of a PMOS transistor to a power supply voltage Vdd terminal, a wiring 104b for outputting a signal OUT from the drains of PMOS and NMOS transistors, a wiring 104c for connecting the source of the NMOS transistor to a ground voltage Vss terminal, and a wiring 104d for inputting a signal IN to the gate electrode 103.
The respective source or drain impurity diffusion layers are connected to the wirings 104a to 104d through contact holes 105 formed in the interlayer dielectric film.
A well boundary 107 exists to isolate the conductivity types of the PMOS transistor region 101 and NMOS transistor region 102. The inside of a region 108 enclosed with the dotted line is a region ion-implanted with an N-type impurity. The outside of the region 108 is a region ion-implanted with a P-type impurity.
In the inverter having this arrangement, the source side of the PMOS transistor region 101 is connected to the power supply voltage Vdd terminal, the source side of the NMOS transistor is connected to the ground potential Vss terminal, a signal IN100 is input to the gate electrode 103 of the PMOS and NMOS transistors, and the signal OUT is output from the drain side of the PMOS and NMOS transistors.
FIG. 12 shows the circuit arrangement of a NAND circuit based on a CMOS arrangement. This circuit uses PMOS transistors 1201 and 1202 and NMOS transistors 1203 and 1204. A signal IN1 is input to the gates of the PMOS transistor 1201 and NMOS transistor 1204. A signal IN2 is input to the gates of the PMOS transistor 1202 and NMOS transistor 1203. The signal OUT is output from the drains of the PMOS transistors 1201 and 1202.
FIG. 13 shows an example of a conventional layout that realizes this NAND circuit.
PMOS transistor regions 201 and 202 are formed, and gate electrodes 203a and 203b are formed on the channel regions of the respective transistor regions through a gate insulating film.
NMOS transistor regions 204 and 203 are formed, and the gate electrodes 203a and 203b extend on the channel regions of the respective transistor regions.
A power supply voltage Vdd line 204a and ground voltage Vss line 204b are arranged on the upper and lower sides along one direction in FIG. 13. Wirings 204d and 204e are provided on the source regions of the PMOS transistor regions 201 and 202, and both are connected to the power supply voltage Vdd line 204a. A wiring 204f is commonly formed on the drain regions of the PMOS transistor regions 201 and 202, and extends on the drain region of the NMOS transistor 203. A wiring 204g formed on the source region of the NMOS transistor 204 is connected to the ground voltage Vss line 204b. 
Note that the following are references that disclose conventional techniques:                reference 1: U.S. Ser. No. 2001/0019162        reference 2: U.S. Pat. No. 6,114,903        reference 3: Japanese Patent Laid-Open No. 05-259398        reference 4: Japanese Patent Laid-Open No. 07-130971        
The following problems are, however, posed in the conventional semiconductor integrated circuits.
A distance 109 exists between the PMOS transistor region 101 and the NMOS transistor region 102 shown in FIG. 11. Likewise, a distance 209 exists between the PMOS transistor region 201 and the NMOS transistor region 204 shown in FIG. 13. For example, the distance 109 is determined from the sum of the distance required from the PMOS transistor region 101 to a well boundary 107 and the distance required from the NMOS transistor region 102 to the well boundary 107.
A PN junction is formed on the well boundary 107 by bringing an N-type impurity diffusion layer on which the PMOS transistor region 101 is formed into contact with a P-type impurity diffusion layer on which the NMOS transistor region 102 is formed.
Both the P- and N-type impurity profiles are not constant near the well boundary 107 to result in a density gradient. When the well boundary 107 and the channel region of each transistor come so close to each other as to be affected by the density gradient, the electrical characteristics of each transistor deteriorate. Therefore, this distance must be set to prevent the influence on transistor characteristics.
In addition, a PNPN thyristor structure is formed between a P-type source/drain region in the PMOS transistor region 101, an N-type impurity diffusion layer on which a PMOS transistor is formed, a P-type impurity diffusion layer on which an NMOS transistor is formed, and an N-type source/drain region in the NMOS transistor region 102.
Bringing the source/drain region of a transistor too close to the well boundary 107 will raise a condition for the operation of this thyristor. As a consequence, latchup occurs. That is, a current always flows from the source region of the PMOS transistor to which a power supply voltage Vdd is applied to the source region of the NMOS transistor to which a ground potential Vss is applied. This causes a circuit operation failure.
In a CMOS circuit, therefore, in order to prevent latchup, the PMOS transistor region 101 must be separated from the NMOS transistor region 102. This has been a bottleneck for higher integration density. This situation also applies to the NAND circuit shown in FIG. 13.